# *******************************************************************************
# Vendor: Xilinx 
# Associated Filename: run_hls.tcl
# Purpose: Tcl commands to setup a Vivado HLS prject 
# Device: All 
# Revision History: March 1, 2013 - initial release
#                                                 
# *******************************************************************************
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##############################################
# Project settings

# Create a project
open_project	-reset hls_prj

# The source file and test bench
add_files	adders.c
add_files -tb	adders_test.c
# Specify the top-level function for synthesis
set_top		adders

###########################
# Solution settings

# Create solution1
open_solution -reset solution1

# Specify a Xilinx device and clock period
# - Do not specify a clock uncertainty (margin)
# - Let the  margin to default to 12.5% of clock period
if ({$::env(FIM_BRD_TYPE)}=="kcu105") {
  set devPart "xcku040-ffva1156-2-e"
  set brdPart "xilinx.com:kcu105:part0:1.5"
} 
if ({$::env(FIM_BRD_TYPE)}=="u50dd") {
  set devPart "xcu50-fsvh2104-2L-e"
  set brdPart "xilinx.com:au50dd:part0:1.0"
}
set_part $devPart
create_clock -period 3.25
#set_clock_uncertainty 1.25

# Simulate the C code 
csim_design

# Synthesis the C code
csynth_design


# Co-Simulate the C code
cosim_design -trace_level all -rtl verilog

# Export design to IPI
export_design

exit

